A Random Compensation Scheme for 5G Slicing Under Statistical Delay-QoS Constraints
نویسندگان
چکیده
منابع مشابه
A New Method for Time-Delay Compensation in Control Systems
In this paper a new method is introduced and investigated for removing the destabilizing effects of time-delay parameter in control loops. The concept of the method is taken from the knowledge concerning the dynamic behaviour of irrational transfer functions (Ir-TF), which is discussed and investigated elswhere in frequency response domain and is explained briefly here. Ir-TFs, which are we...
متن کاملOptimum hybrid error correction scheme under strict delay constraints
ixcalled Gilbert-Elliott (GE) channel model [Mus89] with the two-state Markov chain was proved to be adequate for modeling the frame losses in slow fading channels and the burst packet losses in Wireless LANs such as IEEE 802.11a and IEEE 802.11b and so on. In this thesis, therefore, we will adopt the GE channel model as the erasure error channel model to evaluate the performance of all kinds o...
متن کاملPower Minimization under QoS Constraints
QoS has been often addressed in multimedia, video, and networking research communities, but rarely in the design community. Our goal is to introduce the rst system design technique for comprehensive quality-of-service (QoS) low power synthesis. Speci cally, we study how to e ciently exploit the trade-o between the system cost and energy consumption in real-time systems that address packet-based...
متن کاملReference Chaser Bandwidth Controller for Wireless QoS Mapping under Delay Constraints
Telecommunications networks are composed of functional layers acting in cascade. Quality of Service (QoS) derives from the action of each layer that must assure a specific level of quality to the upper layer in terms of performance parameters (e.g., loss, delay, jitter of the packets). Appropriate algorithms are needed to compute the bandwidth necessary so to assure the requested QoS when infor...
متن کاملA low-glitch binary-weighted DAC with delay compensation scheme
This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted currentsteering digital-to-analog converter (DAC). Instead of using large input buffers to drive a lot of current switches and re-timing latches, the proposed design uses variabledelay buffers with a compact layout to compensate for the delay difference among different bits, and to reduce glitch ener...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEEE Access
سال: 2020
ISSN: 2169-3536
DOI: 10.1109/access.2020.3033321